Contact

benoit.dinechin@gmail.com

Benoît Dupont de Dinechin on ResearchGate

Education

• Engineer from the École Nationale Supérieure de l'Aéronautique et de l'Espace (ENSAE), Toulouse, France in 1985.

• Master of Science in Computer Systems from the Université Paul Sabatier, Toulouse, France, in 1986.

• PhD in Computer Science from the Université de Paris 6, laboratoire MASI, Paris, France, in 1991.

• Invited scientist at the McGill University, School of Computer Science, Montréal, Canada, in 1995 and 1996.

Career Outline

• Commissariat a l'Energie Atomique, Direction des Applications Militaires, France, from 1989 to mid 1998.

• Part-time consultant at Cray Research Inc., Minnesota, USA, from 1992 to 1997.

• Software engineer at STMicroelectronics Grenoble, France, from mid-1998 to mid-2004.

• Research engineer at STMicroelectronics Manno, Switzerland, from mid-2004 to mid-2007.

• Research and Development responsible at STMicroelectronics Grenoble, France, from mid-2007 to early 2009.

• STMicroelectronics National Fellow in November 2008.

• Compiler team leader and company fellow at Kalray in February 2009.

• Director of software development at Kalray in February 2012.

• Chief Technology Officer at Kalray since March 2013.

Contributions

• Designed and developed the software pipeliner for the Cray T3E production compilers.

• Contributed to the design of Cray F--, the first PGAS language and the ancestor of Co-Array Fortran.

• Led the development of the linear assembly optimizer (LAO) for the STMicroelectronics ST120 VLIW-DSP core.

• Led the development of the production compiler for the STMicroelectronics ST200 VLIW family based on the Open64 and a SSA-based code generator.

• Designed and developed the Machine Description System (MDS) used by STMicroelectronics production compilation tools.

• Initiated the STMicroelectronics Manno project that established the applicability of CLI program representation (.NET byte code) to C media processing using JIT compilation on VLIW cores.

• Architected the Kalray VLIW core and co-architected the Kalray 1st-generation massively parallel processing array (MPPA) processors.

• Led the development of software tools and run-time libraries of the 1st-generation MPPA processor, in the areas of cyclostatic dataflow and explicit parallel programming models.

• Advanced the architecture and programming models of the 2nd-generation MPPA processor for the support of time-critical applications.

• Designed the NoC guaranteed services framework of the 2nd-generation MPPA processor based on deterministic network calculus.

• Designed the security architecture of the 3rd-generation MPPA processor to meet defense, avionics and automotive security requirements.

• Architected the deep learning coprocessors of the two 3rd-generation MPPA processors.

• Improved the GCC port to the KVX (Kalray VLIW architectures) in the areas of FP16 support, if-conversion, SIMD instruction selection, builtin types and functions, hardware loop mapping, instruction scheduling and bundling.

• Member of the EU CoreNect Expert Group #1 Compute & Store (COREnect is a consortium formed to develop a beyond 5G and 6G strategic roadmap for future European connectivity systems and components).

• Kalray representative at the OpenHW Group.

Bibliography

Books and Journals

• Benoît Dupont de Dinechin "A Qualitative Approach to Many-core Architecture" in "Multi-Processor System-on-Chip 1 Architectures" ISBN : 9781789450217, March 2021.

• Marco Cococcioni, Federico Rossi, Emanuele Ruffaldi, Sergio Saponara, Benoît Dupont de Dinechin "Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities" IEEE Signal Process. Mag. 38(1): 97-110, 2021.

• Marc Boyer, Amaury Graillat, Benoît Dupont de Dinechin, Jörn Migge "Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks" Performance Evaluation 143: 102124, 2020.

• Georgia Giannopoulou, Peter Poplavko, Dario Socci, Pengcheng Huang, Nikolay Stoimenov, Paraskevas Bourgos, Lothar Thiele, Marius Bozga, Saddek Bensalem, Sylvain Girbal, Madeleine Faugere, Romain Soulat, Benoît Dupont de Dinechin "DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems" Design Automation for Embedded Systems, Springer 2018. 

• Vanessa Vargas, Pablo Ramos, Vincent Ray, Camille Jalier, Renaud Stevens, Benoît Dupont De Dinechin, Maud Baylac, Francesca Villa, Solenne Rey, Nacer-Eddine Zergainoh, Jean-Francois Méhaut, Raoul Velazco "Radiation Experiments on a 28 nm Single-Chip Many-Core Processor and SEU Error-Rate Prediction". IEEE Transactions on Nuclear Science, 64(1) (January 2017).

• Georgia Giannopoulou, Nikolay Stoimenov, Pengcheng Huang, Lothar Thiele, Benoît Dupont de Dinechin "Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources", Real-Time Systems vol. 52, pp. 399–449 (July 2016).

• Benoît Dupont de Dinechin, Alix Munier‑Kordon "Converging to Periodic Schedules for Cyclic Scheduling Problems with Resources and Deadlines", Computers & Operations Research, vol. 51, pp. 227-236 (2014).

• Alix Munier‑Kordon, Fadi Kacem, Benoît Dupont de Dinechin, Lucian Finta "Scheduling an interval ordered precedence graph with communication delays and a limited number of processors", RAIRO-Oper. Res. 47 (2013) 73–87.

• Dibyendu Das, Benoît Dupont de Dinechin, Ramakrishna Upadrasta "Efficient liveness computation using merge sets and DJ-graphs" TACO 8(4): 27 (2012).

• Sid Ahmed Ali Touati, Frédéric Brault, Karine Deschinkel, Benoît Dupont de Dinechin "Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types" ACM Trans. Embedded Comput. Syst. 10(4): 47 (2011).

• Benoit Dupont-de-Dinechin, Christian Artigues, Sadia Azem "Resource-Constrained Modulo Scheduling" Resource-Constrained Project Scheduling: Models, Algorithms, Extensions and Applications, January 2008.

• Benoît Dupont de Dinechin "From Machine Scheduling to VLIW Instruction Scheduling" ST Journal of Research Volume 1, Number 2, September 2004.

• Benoît Dupont de Dinechin, Christophe Monat, Patrick Blouet, Christian Bertin "DSP-MCU Processor Optimization for Portable Applications" Microelectronic Engineering Volume 54 Issue 1, December 2000.

Conference Papers

• Benoît Dupont de Dinechin, Julien Hascoët, Orégane Desrentes "In-Place Multi-Core SIMD FFTs",  27th Annual IEEE High Performance Extreme Computing Virtual Conference (HPEC), September 2023.

• Orégane Desrentes, Benoît Dupont de Dinechin, Florent de Dinechin "Exact Fused Dot Product Add Operators", 30th IEEE International Symposium on Computer Arithmetic (ARITH), September 2023.

• Orégane Desrentes, Benoît Dupont de Dinechin, Julien Le Maire "Exact Dot Product Accumulate Operators for 8-bit Floating-Point Deep Learning", 26th Euromicro Conference on Digital System Design (DSD), September 2023.

• Benoît Dupont de Dinechin "Computing In-Place FFTs with SIMD Lane Slicing", 26th Annual IEEE High Performance Extreme Computing Virtual Conference (HPEC), September 2022.

• Orégane Desrentes, Diana Resmerita, Benoît Dupont de Dinechin "A Posit8 Decompression Operator for Deep Neural Network Inference", Conference on Next-Generation Arithmetic 2022 (part of Supercomputing Asia 2022), March 2022.

• Diana Resmerita, Rodrigo Cabral Farias, Lionel Fillatre, Benoît Dupont de Dinechin "Classification Error Approximation of a Compressed Linear Softmax Layer" 29th European Signal Processing Conference (EUSIPCO 2021),  August 2021.

• Matheus Schuh, Claire Maiza, Joël Goossens, Pascal Raymond, Benoît Dupont de Dinechin "A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory" 41st IEEE Real-Time Systems Symposium (RTSS 2020), December 1 – 4, 2020.

• Diana Resmerita, Rodrigo Cabral Farias, Benoît Dupont de Dinechin, Lionel Fillatre "Benchmarking Alternative Floating-Point Formats for Deep Learning Inference" Compas’2020, Lyon, France,  July 2020.

• Benoît Dupont de Dinechin "Deep Learning Inference on the MPPA3 Manycore Processor" Embedded World Conference, Nuremberg, Germany, February 25 - 27 2020.

• Amaury Graillat, Claire Maiza, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin "Response Time Analysis of Dataflow Applications on a Many-Core Processor with Shared-Memory and Network-on-Chip"  RTNS 2019 / 27th International Conference on Real-Time Networks and Systems, Toulouse, France, November 2019.

• Diana Resmerita, Rodrigo Cabral Farias, Benoît Dupont de Dinechin, Lionel Fillatre "Compression des réseaux de neurones profonds à base de quantification uniforme et non-uniforme" Colloque GRETSI, Aug 2019, Lille, France.

• Benoît Dupont de Dinechin "Consolidating High-Integrity, High-Performance, and Cyber-Security Functions on a Manycore Processor" DAC '19- Proceedings of the 56th Annual Design Automation Conference, Las Vegas, Nevada, June 2019.

• Julien Hascoët, Benoît Dupont de Dinechin, Karol Desnos, Jean-Francois Nezan "A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore" IEEE High Performance Extreme Computing Conference (HPEC ‘18) Waltham, MA USA, September 2018 (Best Student Paper).

• Amaury Graillat, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin "Parallel Code Generation of Synchronous Programs for a Many-core Architecture" Design, Automation and Test in Europe (DATE 2018), Dresden, Germany, March 2018.

• Hugo Miomandre, Julien Hascoët, Karol Desnos, Kevin Martin, Benoît Dupont de Dinechin, Jean-François Nezan "Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures" 9th Workshop and 7th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM '18), Manchester, United Kingdom, January 2018.

• Marc Boyer, Benoît Dupont de Dinechin, Amaury Graillat, Lionel Havet "Computing Routes and Delay Bounds for the Network-on-Chip of the Kalray MPPA2 Processor" European Congress on Embedded Real-Time Software (ERTS 2018), Toulouse, France, January 2018.

• Minh Quan Ho, Christian Obrecht, Bernard Tourancheau, Benoît Dupont de Dinechin, Julien Hascoet "Improving 3D lattice boltzmann method stencil with asynchronous transfers on many-core processors" IEEE 36th International Performance Computing and Communications Conference (IPCCC),  San Diego, CA, USA, December 2017.

• Benoît Dupont de Dinechin, Amaury Graillat "Feed-Forward Routing for the Wormhole Switching Network-on-Chip of the Kalray MPPA2-256 Processor" 10th International Workshop on Network-on-Chip Architectures (NoCArc 2017), Boston, MA, USA, November 2017.

• Julien Hascoët, Benoît Dupont de Dinechin, Pierre Guironnet de Massas, Minh-Quan Ho "Asynchronous One-Sided Communications and Synchronizations for a Clustered Manycore Processor" 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia 2017), Seoul, South Korea, October 2017.

• Alvise Rigo, Christian Pinto, Kevin Pouget, Daniel Raho, Denis Dutoit, Pierre-Yves Martinez, Chris Doran, Luca Benini, Iakovos Mavroidis, Manolis Marazakis, Valeria Bartsch, Guy Lonsdale, Antoniu Pop, John Goodacre, Annaik Colliot, Paul M. Carpenter, Petar Radojkovic, Dirk Pleiter, Dominique Drouin, Benoît Dupont de Dinechin "Paving the way towards a highly energy-efficient and highly integrated compute node for the Exascale revolution: the ExaNoDe approach" Euromicro Symposium on Digital System Design (DSD 2017), Vienna, Austria, September 2017.

• Julien Hascoët, Karol Desnos, Jean-François Nezan, Benoît Dupont de Dinechin "Hierarchical Dataflow Model for Efficient Programming of Clustered Many-Core Processors" ASAP 2017, July 10th-12th 2017, Seattle, WA, USA.

• Benoît Dupont de Dinechin, Amaury Graillat "Network-on-Chip Service Guarantees on the Kalray MPPA-256 Bostan Processor" 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing System (AISTECS 2017), Stockholm, Sweden, January 2017.

• Bruno Bodin, Alix Munier Kordon, Benoît Dupont de Dinechin "Optimal and Fast Throughput Evaluation of CSDF" Proceedings of the 53rd Annual Design Automation Conference DAC '16, June 5-9 2016, Austin, Texas, USA (HiPEAC Paper Award).

• Selma Saidi, Rolf Ernst, Sascha Uhrig, Henrik Theiling, Benoît Dupont de Dinechin "The Shift to Multicores in Real-Time and Safety-Critical Systems" CODES+ISSS 2015 invited paper, October 4–9 2015, Amsterdam, The Netherlands.

• Julien Hascoët, Andrew Ensor, Jean-François Nezan, Benoît Dupont De Dinechin "Implementation of a Fast Fourier Transform onto a Manycore Embedded System" DASIP 2015, September 23–25 2015, Cracow, Poland.

• Minh Quan Ho, Bernard Tourancheau, Christian Obrecht, Benoît Dupont de Dinechin, Jérôme Reybert "MPI Communication on MPPA Many-Core NoC: Design, Modeling and Performance Issues" PARCO 2015, 1-4 September 2015, Edinburgh, Scotland (UK).

• Benoît Dupont de Dinechin, Yves Durand, Duco van Amstel, Alexandre Ghiti "Guaranteed Services of the NoC of a Manycore Processor" NoCArc 2014, December 13rd 2014, Cambridge, U.K.

• Benoît Dupont de Dinechin “Using the SSA-Form in a Code Generator" CC 2014 invited paper, LNCS 8409, pp. 1–17, 2014.

• Benoît Dupont de Dinechin, Duco van Amstel, Marc Poulhiès, Guillaume Lager  “Time-Critical Computing on a Single-Chip Massively Parallel Processor" DATE 2014 invited paper for special session SD1 “Predictable Multi-Core Computing", 24-28 March 2014, Dresden, Germany.

• Bruno Bodin, Alix Munier‑Kordon, Benoît Dupont de Dinechin “Periodic Schedules for Cyclo-Static Dataflow" ESTIMedia 2013: Symposium on Embedded Systems for Real-Time Multimedia, Embedded Systems Week, September 29 – October 4, 2013, Montreal.

• Benoît Dupont de Dinechin, Renaud Ayrignac, Pierre-Edouard Beaucamps, Patrice Couvert, Francois Jacquet, Samuel Jones, Nicolas Morey Chaisemartin, Frederic Riss, Thierry Strudel "A Clustered Manycore Processor Architecture for Embedded and Accelerated Applications" IEEE HPEC'13, September 2013, Waltham, MA USA.

• Benoît Dupont de Dinechin, Pierre Guironnet de Massas, Guillaume Lager, Clément Léger, Benjamin Orgogozo, Jérôme Reybert and Thierry Strudel "A Distributed Run-Time Environment for the Kalray MPPA-256 Integrated Manycore Processor", ICCS 2013 ALCHEMY Workshop, June 2013.

• Pascal Aubry, Pierre-Edouard Beaucamps, Frédéric Blanc, Bruno Bodin, Sergiu Carpov, Loïc Cudennec, Vincent David, Philippe Dore, Paul Dubrulle, Benoît Dupont de Dinechin, François Galea, Thierry Goubier, Michel Harrand, Samuel Jones, Jean-Denis Lesage, Stéphane Louise, Nicolas Morey Chaisemartin, Thanh Hai Nguyen, Xavier Raynaud and Renaud Sirdey "Extended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor", ICCS 2013 ALCHEMY Workshop, June 2013.

• Benoît Dupont de Dinechin, Julien Villette, Ayrignac Renaud, Vincent Ray et Nicolas Brunie "Conception et mise en œuvre d’une architecture VLIW pour le calcul embarqué", ComPAS'13, January 2013.

• Nicolas Brunie, Florent De Dinechin et Benoît De Dinechin "Conception d’une matrice reconfigurable pour coprocesseur fortement couplé", ComPAS'13, January 2013.

• Bruno Bodin, Alix Munier‑Kordon, Benoît Dupont de Dinechin “K-Periodic Schedules for Evaluating the Maximum Throughput of a Synchronous Dataflow Graph”, SAMOS Inter. Conf. on Embedded Computer Systems, vol. 12, 2012.

• Nicolas Brunie, Florent de Dinechin, and Benoît Dupont de Dinechin "A mixed-precision fused multiply and add" 45th Asilomar Conference on Signals, Systems & Computers, 2011.

• Benoit Boissinot, Florian Brandner, Alain Darte, Benoît Dupont de Dinechin, Fabrice Rastello "A Non-iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs" Programming Languages and Systems - 9th Asian Symposium APLAS 2011.

• Frédéric Brault, Benoît Dupont de Dinechin, Sid Ahmed Ali Touati, Albert Cohen "Software Pipelining and Register Pressure in VLIW Architectures" ODES 2010.

• Benoit Boissinot, Alain Darte, Fabrice Rastello, Benoît Dupont de Dinechin, Christophe Guillon "Revisiting Out-of-SSA Translation for Correctness, Code Quality, and Efficiency (Best Paper)" CGO 2009.

• Benoît Dupont de Dinechin "Inter-Block Scoreboard Scheduling in a JIT Compiler for VLIW Processors" Euro-Par 2008 (with slides).

• Benoit Boissinot, Sebastian Hack, Daniel Grund, Benoît Dupont de Dinechin, Fabrice Rastello "Fast Liveness Checking for SSA-Form Programs (Best Paper)" CGO 2008 (with slides).

• Benoît Dupont de Dinechin "Scheduling Monotone Interval Orders on Typed Task Systems" PlanSIG 2007 (with slides).

• Benoît Dupont de Dinechin "Time-Indexed Formulations and a Large Neighborhood Search for the Resource-Constrained Modulo Scheduling Problem" MISTA 2007 (with slides).

• Sadia Azem, Benoit Dupont-de-Dinechin, Christian Artigues "Résolution d'un problème d'ordonnancement modulo sur une architecture VLIW par la programmation linéaire en nombre entiers" ROADEF 2006 (with slides).

• Florent Blachot, Benoît Dupont de Dinechin, Guillaume Huard "SCAN: a Heuristic for Near-Optimal Software Pipelining" Euro-Par 2006.

• Jean-Michel Muller, Arnaud Tisserand, Benoît Dupont de Dinechin, Christophe Monat "Division by Constant for the ST100 DSP Microprocessor" ARITH 2005.

• Christian Bertin, Nicolas Brisebarre, Benoît Dupont de Dinechin, C.-P. Jeannerod, C. Monat, J.-M. Muller, S.K. Raina and A. Tisserand "A Floating-Point Library for Integer Processors" SPIE 2004.

• Benoît Dupont de Dinechin "Modulo Scheduling with Regular Unwinding" DOM 2004 (with slides).

• Benoît Dupont de Dinechin, Christophe Monat, Fabrice Rastello "Parallel Execution of the Saturated Reductions" SIPS 2001.

• Benoît Dupont de Dinechin, François de Ferrière, Christophe Guillon, Artour Stoutchinin "Code Generator Optimizations for the ST120 DSP-MCU Core" CASES 2000.

• Benoît Dupont de Dinechin "Extending Modulo Scheduling with Memory Reference Merging" CC 1999.

• Benoît Dupont de Dinechin "A Unified Software Pipeline Construction Scheme for Modulo Scheduled Loops" PaCT 1997.

• Robert W. Numrich, Jon L. Steidel, Brian H. Johnson, Benoît Dupont de Dinechin, Gary Elsesser, Greg Fischer, Tom MacDonald "Definition of the F-- Extension to Fortran 90" LCPC 1997.

• Benoît Dupont de Dinechin "Parametric Computation of Margins and of Minimum Cumulative Register Lifetime Dates" LCPC 1996.

• Benoît Dupont de Dinechin "Insertion Scheduling: An Alternative to List Scheduling for Modulo Schedulers" LCPC 1995.

• Benoît Dupont de Dinechin "An Introduction to Simplex Scheduling" PACT 1994.

• Benoît Dupont de Dinechin "StaCS: a Static Control Superscalar Architecture" MICRO 1992.

• Benoît Dupont de Dinechin "An Ultra-Fast Euclidean Division Algorithm for Prime Memory Systems" ICS 1991.

Technical Reports

(whenever significantly different from otherwise published work)

• Benoît Dupont de Dinechin "Inter-Block Scoreboard Scheduling in a JIT Compiler for VLIW Processors" A/392/CRI 2008.

• Benoît Dupont de Dinechin "The Regular Unwinding Framework" E/280/CRI 2006.

• Benoît Dupont de Dinechin "From Machine Scheduling to VLIW Instruction Scheduling" A/352/CRI 2003.

• Benoît Dupont de Dinechin "Software Pipelining on the Cray MPP: History, Status and Perspectives" Cray CEA 1997.

• Benoît Dupont de Dinechin "Fast Modulo Scheduling under the Simplex Scheduling Framework" PRISM-01 1995.

• Benoît Dupont de Dinechin "Simplex Scheduling: More than Lifetime-Sensitive Instruction Scheduling" PRISM-22 1994.

• Benoît Dupont de Dinechin "Parallélisation de code et architectures superscalaires à controle statique" PhD Thesis 1991.

Hardware Patents

• Orégane Desrentes, Benoît Dupont de Dinechin "Exact Fused Dot-Product Add Operators"

• Julien Le Maire, Benoît Dupont de Dinechin, Arnaud Odinot "Hybrid Multiply-Accumulate Operator"

• Benoît Dupont de Dinechin "Indexing a buffer in a register file" Filed in FR22 02950.

• Benoît Dupont de Dinechin "Dual-multiply dual-add operator for 3- or 4-address instruction sets" Filed FR20 14208.

• Benoît Dupont de Dinechin, Julien Le Maire "System for Processing Matrices Using Multiple Processors Simultaneously" Filed FR20 14301.

• Pierre Guironnet de Massas, Vincent Ray, Benoît Dupont de Dinechin "Allocation of execution resources to privilege levels in a processor" Published US2021/0200904 .

• Benoît Dupont de Dinechin, Arnaud Odinot, Vincent Ray "Configurable Inter-Processor Synchronization System" Published FR3091363 (A1) ― 2020-07-03.

• Benoît Dupont de Dinechin, Julien Le Maire, Nicolas Brunie "System for Multiplying Matrices by Blocks" Published FR3090932 (A1) ― 2020-06-26.

• Benoît Dupont de Dinechin, Marta Rybczynska, Vincent Ray "Atomic Instruction Having  a Local Scope Scoped to an Intermediate Cache Level" Published FR3048526 (A1) ― 2017-09-08.

• Duco van Amstel, Alexandre Blampey, Benoît Dupont de Dinechin "Token Bucket Flow-Rate Limiter" Published 2017/0149908.

• Thomas Champseix, Benoît Dupont de Dinechin, Pierre Guironnet de Massas "Hardware Synchronization Barrier Between Processing Units" US2015339173

• Benoît Dupont de Dinechin, Vincent Ray "Inter-Processor Synchronization System" US2015339256.

• Renaud Ayrignac,  Vincent Ray, Benoît Dupont de Dinechin "VLIW Type Instruction Packet Structure and Processor Suitable for Processing Such an Instruction Packet" WO2015177427.

• Benoît Dupont de Dinechin, Marta Rybczynska "Bit Matrix Multiplication Using Explicit Registers" EP2947562, US2015339101.

• Michel Harrand, Yves Durand, Patrice Couvert, Thomas Champseix, Benoît Dupont de Dinechin "Stream Management in an On-Chip Network" EP2771800, US2014301205.

• Florent Dupont de Dinechin, Nicolas Brunie, Benoît Dupont de Dinechin "Mixed Precision Fused Multiply Accumulator" EP2702478,  US2014089371.

• Benoît Dupont de Dinechin "Opérateur saturant à haute efficacité" EU 03354010.

• Benoît Dupont de Dinechin "Dispositif et procédé d'arbitrage des requêtes et de résolution des conflits lies à l'accès aux mémoires à bancs indépendants" FR 89 00689.

Presentations

Keynote & Invited Presentations

• SC Asia / CoNGA 2023 "Posit Arithmetic in the European Processor Initiative", March 2023.

• MPSoC 2022 "Deep Learning Inference Support on the MPPA3 V2 Processor", June 2022.

• FETCH 2022 "A CPU-Based Manycore Architecture for Deep Learning Inference", June 2022.

• COREnect 3rd Workshop "Manycore Acceleration for 5G Infrastructure and Edge Computing", February 2022.

• HiPEAC CSW Autumn 2021 keynote "Co-Design of the Kalray Manycore Accelerator for Edge Computing",  October 2021.

• CPS&IoT’2021 keynote "Engineering a Manycore Processor for Accelerated Edge Computing", June 2021.

• Embedded Multicore Summit Japan "Consolidating High-Integrity and High-Performance Functions on a Manycore Processor", November 2020.

• TU Darmstadt Colloquium "Consolidating High-Integrity and High-Performance Functions on a Manycore Processor", July 2020.

• IEEE Int. Conference on New Circuits and Systems (NEWCAS 2019) - Keynote "MPPA® Manycore Processor: At the heart of Intelligent Systems", Munich, Germany, June 2019.

• 56th Annual Design Automation Conference (DAC) 2019 "Consolidating High-Integrity, High-Performance, and Cyber-Security Functions on a Manycore Processor",  Las Vegas, USA, June 2019.

• 32nd International Conference on Architecture of Computing Systems (ARCS) 2019 "MPPA® Manycore Processor: At the Heart of Intelligent Systems"  Copenhagen, Denmark, May 2019.

• Embedded-SEC18 "Securing the Kalray MPPA® Manycore Architecture" December 7th 2018 , Paris, France.

• ANF CNRS DAQ 2018 "Parallel Processing with the MPPA® Manycore Processor" November 14 2018, Fréjus, France.

• 16th International System-on-Chip (SoC) Conference, Exhibit & Workshops "Kalray’s MPPA3 Manycore Processor: At the Heart of Intelligent Systems",  October 17 & 18 2018, University of California, Irvine, USA.

• 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018) "Co-Design and Abstraction of a Network-on-Chip Using Deterministic Network Calculus", October 4 – 5 2018, Torino, Italy.

• Adaptive Many-Core Architectures and Systems workshop "Manycore Accelerators beyond GPU Architecture", June 13-15th 2018, York, UK.

• Supercomputing Frontiers Europe 2018 "Manycore Accelerators beyond GPU Architecture", March 12 – 15, 2018, Warsaw, Poland.

• AK Multicore Event "Engineering a Manycore Processor for Embedded High-Performance Computing", October 23rd 2017, Munich, Germany.

• Autonomous Vehicle Software Symposium 2017 "Supporting Standard CNN Inference on Manycore Processors", June 20-21 2017, Stuttgart, Germany.

• AutoSens Conference 2017 "Manycore Processing for Vehicle Perception Functions", May 22-25 2017, M1 Concourse, Detroit MI, USA.

• Digital Innovation Forum 2017, "Kalray’s MPPA® processors to find their way into cars, drones and aerospace" (Innovation session on Smart Mobility Award), May 10-11, 2017, Amsterdam, Netherlands.

• MCSOC 2016 "Engineering a Manycore Processor Platform for Mission-Critical Applications", September 21st-23rd 2016, Lyon, France.

• ECRTS16 / RTN'2016 "Guaranteed Services of the NoC and DDR Memory of the MPPA Processor", July 5th-8th 2016, Toulouse, France.

• EMS 2015 "The MPPA-256 Bostan Manycore Processor for Real-Time and Safety-Critical Systems", November 19th, 2015, Yokohama, Japan.

• COOL Chips XVIII "The Kalray MPPA Mission-Critical Supercomputer on a Chip" April 13-15, 2015, Yokohama, Japan.

• CC 2014 (Compiler Construction) "Using the SSA Form in a Code Generator", April 9th 2014, Grenoble, France.

• DATE 2014 System Level Design session "Time-Critical Computing on a Single Chip Massively Parallel Processor", March 26th 2014, Dresden, Germany.

• INA-OMC 2014 8th Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC) "Guaranted Services on the Network-on-Chip of the Kalray MPPA Single Chip Manycore Processor" in conjunction with the HiPEAC 2014 conference, January 22nd 2014, Vienna, Austria.

• MCC 2013 "Architecture and Programming Models of the Kalray MPPA Single Chip Manycore Processor", November 26th 2013, Halmstad, Sweden.

• DASIP 2013 "Latency-Constrained Image and Signal Processing on a Manycore Processor" October 8th 2013, Cagliari, Italy.

• MuCoCoS 2013 "Dataflow Language Compilation for a Single Chip Massively Parallel Processor", September 7th, 2013, Edinburgh, Scotland, UK.

• HiPEAC 2013 "Integrating a distributed memory computer on a chip: challenges and opportunities" January 23rd 2013, Berlin, Germany.

• ComPAS 2013 "L’interface des réseaux sur puce: une nouvelle frontière architecturale" January 18th 2013, Montbonnot, France.

• GREPS 2007 "GCC for Embedded VLIW Processors: Why Not?"

Workshop Presentations

• GNU Cauldron 2022 "If-Conversion for a Partially Predicated VLIW Architecture", September 16-19th 2022, Prague, Czech Republic.

• Dagstuhl Seminar 18092 "The Logical Execution Time Paradigm: New Perspectives for Multicore Systems" "Embedded HPC with MPPA® Manycore Processors", February 25 – 28 , 2018, Germany.

• HiPEAC CSW 2017 "Accelerating Standard CNN Inference on Many-core Processors", October 25-27 2017, Stuttgart, Germany.

• ETR 2017 "Service Guarantees for the Wormhole Switching NoC of the MPPA-256 Bostan Processor", École d'Été Temps Réel, 28 août-1 sept. 2017 Paris, France.

• DATE 2017 W07 "Consolidating High-Performance and High-Integrity Autonomous Driving Functions on the MPPA Manycore Processor", March 31st 2017, Lausanne, Switzerland.

• DATE 2016 W04 "Model-Based Code Generation for the MPPA Manycore Processor" March 18th 2016, Dresden, Germany.

• Hot Chips 27 "Revisiting DSP Acceleration with the Kalray MPPA Manycore Processor" August 24th 2015, Cupertino, CA, USA.

• MPSoC 2013 "Manycore Challenges for the Next Generation of Professional Applications" July 15th 2013, Otsu, Japan.

• HiPEAC 2013 Spring Computing Week "Network-on-Chip Architecture and Run-Time of the MPPA-256 Manycore Processor" (presented by Duco van Amstel), May 5th 2013, Paris, France.

• ARCHI'13 "Architectures Manycœurs", March 29th 2013, Col de Porte, France.

• TORRENTS 2012 "A Distributed Run-Time Environment for an Integrated Manycore Processor" December 12th 2012, Toulouse, France.

• HiPEAC 2012 Autumn Computing Week "Hybrid Bulk Synchronous Programming on and Integrated Manycore Processor" October 16th 2012, Ghent, Belgium.

• COMPEEF 2012 "Explicit Parallel Programming Environment on an Integrated Manycore Processor" September 25th 2012, Grenoble WTC, France.

• HiPEAC 2007 "Inter-Block Scoreboard Scheduling in a JIT Compiler for VLIW processors"

• MIGAS 2000 "DSP-MCU Processor Optimization for Portable Applications"